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Hi Vikram,
Let us think when are the max tran and max cap the worse?
I hope the slew becomes worse in worst corner rather than in best corner.
I am not sure about max cap.
Slew will be worst in worst corner.
In worst corner, Id current flowing through the cell will be very less due to operating conditions. When Id (drain current or drive) is less, it takes longer time to discharge/charge Cout (output cap of cell) + Cin (input cap of next cell connecting to). Since Id is less, delay is more. This delay is cumulative as it passes from cell to cell and results in worst slew.
I believe Max cap/Mac load is constant across the corners. I never heard of operating temperature effecting a capacitance or load value. Correct me if iam wrong and justify your answer.
Why the ASIC designer checks the max cap & max trans violations?
If you look at the liberty file, the timing value is define in an array, function of cap & trans.
If the cap & trans is outside the value define for this array, there is a violation and the tool need to extrapolate the timing value with an internal formula.
But this internal formula is not "perfect" and for huge violation the error/difference with the "real" timing could made an issue.
So for each cap & tran violations, the designer must check the possible impact on the timing and fix them if necessary via ECO step.
I fix the max cap/trans violations in min corner when the violation occurs on a signal/net/pin which is timing concern. Other wise, I don't care.
So, I'm parsing the list to justify or not an ECO fix or not.
This lists are part of our methodology list checks before tapeout.
I want to check with you, let say a net is flagging for max cap violation, which the buffer not able to driver the load of the net, normally we will upsize the buffer, but what will be the impact to a circuit design if we dont fix this max cap violation? How do we really check the impact on this max cap? etc is that to check on RV of the net and so on?
The max cap indicates that the output timing arc does not exist in the table in the liberty file and need to be recalculate with the derivative formula. Higher the violation is higher the relative error (on the timing) will be. Then on this particular net you could check the setup/hold time margins you have to be more confident. Of course if the cap violation is relatively small (less than 10%), and the setup/hold has some margin, you could treated this violation has harmless.
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