matrix multiplication in VHDL

[sougata_vlsi13]

I am doing the matrix multiplication for 1*6 and 6*4 and the output should be 1*4.My check syntax is correct for the code but the output is not coming...please help me in this regard.I am attaching the code.The error is that in output it is taking the value as -2145674,+2145674.please help me to get the output

This is my main module

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.mat_prod.all;

entity mat_mul is
port(clk:in std_logic;
a:in t1;
b:in t2;
produt t3);
end mat_mul;

architecture behav of mat_mul is

begin
process(clk)
begin
-- if(rst='1')then
--prod:=std_logic_vector(0 to 6);
--z<='0';
if(clk'event and clk='1')then
PROD<=matmult(a,b);
end if;
end process;
--z<=prod;
end behav;


my package body as follows:-


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
--use std.standard.all;


package mat_prod is


type t11 is array (0 to 1) of integer;
type t1 is array (0 to 5) of t11; --1*6 matrix
type t22 is array (0 to 5) of integer;
type t2 is array (0 to 3) of t22; --6*4 matrix
type t33 is array (0 to 1) of integer;
type t3 is array (0 to 3) of t33; --1*4 matrix as output


function matmult ( a : t1; b:t2 ) return t3;

end mat_prod;

package body mat_prod is

function matmult ( a : t1; b:t2 ) return t3 is
variable i,j,k : integer:=0;
--variable prod :t3:=(others => (others => (others => '0')));
variable prod :t3:=(others => (others => 0 ));


begin
for i in 0 to 4 loop --(number of rows in the first matrix - 1)
for j in 0 to 4 loop --(number of columns in the second matrix - 1)
for k in 0 to 2 loop --(number of rows in the second matrix - 1)

prod(i)(j) := (prod(i)(j) + (a(i)(k) * b(k)(j)));


end loop;
end loop;
end loop;
return prod;
end matmult;

end mat_prod;

- - - Updated - - -

this is the snapshot of error

 

[TrickyDicky]

you havent run the simulation.
Btw, your design is going to create a lot of parrallel multipliers. are you happy with this?

 

[sougata_vlsi13]

ya i agree but why the output is not coming...i am not getting...i have already supplied the inputs in the modelsim...but still the output is not coming although the check syntax is correct

 

[TrickyDicky]

because you need to run the simulation for at least 1 clock period.