Who have experience in implementing a digital receiver (DDC) in FPGA?
I'm searching books/documents/ etc. etc. about it?
Can anyone help me?
Thanks in advance.
a digital receiver includes many parts, such as downconvert, decimation filter, match filter, AGC, timing recovery device, carrier recovery device, FEC decoder, equalizer, etc.
DDC may be the simplest part. in general, it is only
two or four multipliers(complex multipliers).
For architectural idea's it might be usefull to look at the datasheets of currently available Digital Down Converter IC's form Analog Devices. They give in most cases a lot of nice design details which might help you te set up your own design.
Have a look at the AD6620 at the analog website.