Re: vhdl testbench
Hi everyone,
I also need information on VHDL test benches.
My situation is that I have downloaded Lattice Semiconductors free ispLEVER software and have designed a very simple design with it using schematic/VHDL entry. Now I want to do a functional simulation. But I have no idea how to go about writing and implementing a test bench (I am new to fpga's).
Two things about first ispLEVER
1) they offer a VHDL test bench template (I can click the button to develop one but not sure what to do after that)
2) they offer two choices when it come to simulation Synplify synthesis and Precision synthesis. Is one better than the other?
Any help, tutorials, advice would be greatly appreciated. I don't really know were to start.
Thanks david119