Globally, I do not know. But I have had occasion to build hand-
matched clock trees and rework logic blocks for timing match
when the clock rate relative to natural gate delay made it
necessary.
Standard cell design styles generally depend on there being
a lot of built-in margin, so that you can pretend not to care.
But if you want to squeeze all you can out of a given technology,
there is still full-custom (though not many people want to
design logic using SPICE and adding layout parasitics).