Also, the device mismatch scales roughly as 1/sqrt(Area), so if your circuit is limited by device mismatch, the bigger device area is better.
And, if mismatch is affected by parasitic capacitance mismatch, the larger the design elements, the smaller the effect of parasitic capacitance mismatch, the better.
Also, doing a proper shielding of sensitive elements (such as capacitors in a capacitor bank of SAR ADC) will definitely help - making the area larger.
If it is parasitic resistance limited mismatch - such as difference in resistances and IR drop from power/ground net ports to differential pair "matched" transistors' source of drain pins - it all depends on the quality of the layout (and your ability to detect and debug these mismatches), either larger size or smaller size layout may be better. In general enabling resistance / IR drop matching of large area devices is more complex, and might benefit greatly from using proper software tools for analysis.
As dick_freebird said, if mismatch is limited by large-scale gradients (on-chip temperature, process variation over chip area, etc.) - the smaller size, the better.