stdcell lib
I don't know Ledit SPR ..but early version SPR not support verilog netlist only by
ledit schematic tool format , and for Place & routing
like cellsnake (snake Tech be merge by Caence) need make cell LEF vie
like standard cell maybe like AND2 / Or2 gate
have define cell I/O and which area can not be routing /CROSS
Tanner SPR maybe need redefine cell
If tsmc std cell have 200 cells .. you need redefine 200 cell by you
or use other tool convert , as I know we usually use Ledit for fully layout
not for P&R