how to do place and route in xilinx
SOME DO'S AND DON'Ts TO BE CONSIDER WHILE PLACE AND ROUTE
Flip- flops are almost free in FPGAs
In FPGAs, the area consumed by a design is usually determined by the amount of combinational circuitry, not by the number of ip- ops.
Aim for using 80–90% of the cells on a chip.
If you use more than 90% of the cells on a chip, then the place-and-route program might not be able to route the wires to connect the cells.
If you use less than 80% of the cells, then probably:
there are optimizations that will increase performance and still allow the design to fit on the chip;
or
you spent too much human effort on optimizing for low area;
or
as possible try to ensure that all ip and op use same clock,then clock clock does not impose any constraints on where the place-and-route tool puts ip- ops and gates. If different ip- ops used different clocks,then ip- ops that are near each other would probably be required to use the same clock.
Use only one edge of the clock signal