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Manual Place and route

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sandeep_sggs

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xilinx place and route

Dear all,
Can anybody tell me what is the significance of Manual "place and route" in Xilinx tools ( i Use xilinx9.1) and how to do it in DETAIL! Is manual process really useful considering the Good place and route algorithms embedded in vendor`s tools. i may be wrong, so please rectify me if so is the case!
Any good document for this subject is welcome. plz make it as early as possible..
 

manual place and route

Well dear The scene is just that the Vendor toll is a General tool.ya thats what professional but Designer Interaction Make it more Specific and effecient.
 

place and route

it always helps if at least the design blocks are placed manually (near to their respective IO's).
It reduces the burden on the tool to a large extent and achieve better timing.

Not each and every signal and module needs to be manually handled. A top level manual placement of blocks (guided place and route) result in less run time too.
 

how to do place and route in xilinx

SOME DO'S AND DON'Ts TO BE CONSIDER WHILE PLACE AND ROUTE

Flip- flops are almost free in FPGAs

In FPGAs, the area consumed by a design is usually determined by the amount of combinational circuitry, not by the number of ip- ops.
Aim for using 80–90% of the cells on a chip.

If you use more than 90% of the cells on a chip, then the place-and-route program might not be able to route the wires to connect the cells.

If you use less than 80% of the cells, then probably:
there are optimizations that will increase performance and still allow the design to fit on the chip;
or
you spent too much human effort on optimizing for low area;
or
as possible try to ensure that all ip and op use same clock,then clock clock does not impose any constraints on where the place-and-route tool puts ip- ops and gates. If different ip- ops used different clocks,then ip- ops that are near each other would probably be required to use the same clock.

Use only one edge of the clock signal
 

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