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# Manchester Carry Chain Sizing

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#### solidsnake

##### Newbie level 1
Hi all,
I would like to ask you a question about a (simple, I think) problem that I haven't been able to solve. I am trying to improve my knowledge of adder blocks so, while studying from the Rabaey,Chandrakasan - "Digital Integrated Circuits", I run into an interesting example about how to size a Manchester Carry Chain (represented in the figure below).
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In the book it's pointed out that "the capacitance per node on the carry chain equals four diffusion capacitances (gate-drain or gate-source capacitance), one inverter input capacitance, and the wiring capacitance proportional to the size of the cell. The inverter and the PMOS precharching transistor can be kept at unit size"
Till this points it's all ok, but what I read next makes me a little bit puzzled.

"Together with the wire capacitance, the fixed capacitance can be estimatecd as 15 fF(for our technology). If a unit-sized transistor with width $W_0$ has a resistance of 10 kΩ and a diffusion capacitance of 2fF, then the $RC$ time costant for a chain of transistor of width $W$ is:
$RC = ( 6 fF \cdot \frac{W}{W_0} + 15 fF ) \cdot 10 k\Omega \cdot \frac{W_0}{W}$"

What I don't understand is why in the time constant the total diffusion capacitance is 6 fF instead of 2fF x 4 = 8 fF in that there are 4 diffusion capacitance.