Making a shift register in VHDL

-- 4-bit loadable serial-in and serial-out shift register
--     CLK: in STD_LOGIC;
--     DIN: in STD_LOGIC;
--     LOAD: in STD_LOGIC;
--     LOAD_DATA: in STD_LOGIC_VECTOR(3 downto 0);
--     DOUT: out STD_LOGIC; 
 
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal REG: STD_LOGIC_VECTOR(3 downto 0);
 
--**Insert the following after the 'begin' keyword**
process (CLK)
begin
   if CLK'event and CLK='1' then
   if (LOAD='1') then
     REG <= LOAD_DATA;
   else
        REG <= REG(2 downto 0) & DIN;
   end if;
   end if;
 DOUT <= REG(3);
end process;

-- 4-bit serial-in and parallel-out shift register
--     CLK: in STD_LOGIC;
--     DIN: in STD_LOGIC;
--     DOUT: out STD_LOGIC_VECTOR(3 downto 0);
 
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal REG: STD_LOGIC_VECTOR(3 downto 0);
 
--**Insert the following after the 'begin' keyword**
process (CLK)
begin
   if CLK'event and CLK='1' then  
      REG <= REG(2 downto 0) & DIN;
   end if;
 DOUT <= REG;
end process;

-- 4-bit serial-in and serial-out shift register
--     CLK: in STD_LOGIC;
--     DIN: in STD_LOGIC;
--     DOUT: out STD_LOGIC;
 
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal REG: STD_LOGIC_VECTOR(3 downto 0);
 
--**Insert the following after the 'begin' keyword**
process (CLK)
begin
   if CLK'event and CLK='1' then  
      REG <= REG(2 downto 0) & DIN;
   end if;
 DOUT <= REG(3);
end process;