i have a stuck in coding. firstly, i have create some dictionary. which has 4 value. each value have 8 bit. (i have give the coding at the below) and my problem is i want to declare when the output is 2 bit, it set as 0 and for 8 bit, it set as 1. the declaration has write at the last output bit....
im new in vhdl language.. anyone can help me how to solve this coding?
libraryieee;useieee.std_logic_1164.all;entity COMPRESS isport( clk :inbit;
s :inbit_vector(7downto0);
m :outbit);endentity;architecture dictionary of COMPRESS isBEGINprocess(s)beginif(s <= 0010 0110)then
m <="00";if(s <=11111010)then
m <="01";if(s <= 0110 1100)then
m <="10";if(s <= 0000 0001)then
m <="11";if(s <=OTHERS)then
m <= s;endif;endprocess;