lzw compression technique in VHDL code

[nursafirah]

hi...

i have a stuck in coding. firstly, i have create some dictionary. which has 4 value. each value have 8 bit. (i have give the coding at the below) and my problem is i want to declare when the output is 2 bit, it set as 0 and for 8 bit, it set as 1. the declaration has write at the last output bit....
im new in vhdl language.. anyone can help me how to solve this coding?

coding:

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity COMPRESS is
port (  clk : in bit;
    s   : in bit_vector (7 downto 0);
    m   : out bit );
 
end entity;
architecture dictionary of COMPRESS is
BEGIN
process (s)
begin
 
    if (s <= 0010 0110) then
    m <= "00";
    if (s <= 1111 1010) then
    m <= "01";
    if (s <= 0110 1100) then
    m <= "10";
    if (s <= 0000 0001) then
    m <= "11";
    if (s <= OTHERS) then
    m <= s;
    end if;
end process;

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