I already installed the IBM 90n 9LP design kit from MOSIS and designed an inverter layout to test DRC and LVS checking before starting use this DK.
During LVS running the following error ocurred:
ERROR (AVVSI-10001): Input layout is incomplete. If you still want to continue the run, remove undefined placements from the layout or set '?errorOnMissingMaster nil' option in the RSF-file. (The default value of parameter '?errorOnMissingMaster' is 't'.)
*WARNING* Error while building the VDB
I attached the error window and my Assura LVS configuration window.