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LVDS signal routing, syptoms of reflections

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SamV

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Hi all,

I hope some of you find this interesting..

We have 2 prototypes, one at our company and another using a different hardware platform at another company. The routing of the prototype at the other company has LVDS traces which are >= 15cm, the ADC operates at 250MHZ and were routing the LVDS pairs to an FPGA.

The data from our prototype looks fine, however there are big problems in the data from the other prototype. I know two things about the routing on the prototype at the other company, the pcb/traces are not impedance controlled and the trace lengths between bits (e.g. LVDS bit 9 and LVDS bit 8) may not be length matched. I'm trying to get my head around what the results from the converter after being acquired by the FPGA may look like if there are reflections. After doing a little research I'm thinking reflections may be causing jitter.

I've attached two images, one is sampled data acquired from prototype 1 at our company, the second is sampled data acquired by prototype 2 at the other company. These are digitized waveforms from a nuclear detector. You will notice that one of the two plots has obvious noise issues.

Keeping it simple, please look at the good plot and tell me what I might expect to see different in the basic example of an impedance mismatch (i.e. unknown differential resistance between the + and - differential pairs on the PCB) I'm having a tricky time visualizing this.

Looking at the bad looking plot, does anyone think this looks like what they may have seen before when experiencing LVDS reflection issues? I'd like to say for sure that the problem is something to do with not following the LVDS specs when routing the PCB.

Thanks,

Sam
 

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The plots are of the raw data from the ADC, which I'm assuming has a parallel LVDS output?

I noticed the spacing of the pulses differ between the two plots, and there appears to be a missing third pulse in the second plot. It looks like the data might be 0-4095, which would mean a 12-bit output? based on the level change from what looks like ~2048 down to something around ~1800 I would say you're missing a lot of 1's on bit 9 of the bus. This is purely based on the fact that the proto1 plot has a floor around 2048.

The best way to determine if the reflections are causing this is to use a differential probe on the LVDS pairs and look at an eye diagram of the signals. If you mean horrible signal integrity == jitter then yes that is what looks like is happening.

I don't think I've ever seen data that is that bad over LVDS, did they not route the traces for the LVDS parallel to each other? That's the only thing I can think of by the statement they did not control the impedance. The other prototype needs a board respin. Or better yet find a better company (with competent people) to work with.
 

marce

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I agree, if LVDS signals are not routed correctly there is no point using LVDS, the whole point is a balanced signal and balanced routing, that means close coupled pairs with minimum difference in length.
To not route the signals correctly is usually down to one of several causes:
1. They were not informed that the signals were LVDS and required routing as such...
2. They were informed and did not do it, either missed one pair by mistake, checking should have picked this up, mistakes do happen.
3. They are muppets go to a reputable company.
 

FvM

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Relating the apparently incorrect received ADC output to LVDS signal quality isn't but an unsubstantiated guess, I think. There could be a lot of different design problems causing the shown picture, e.g. FPGA timing issues.

I understood so far that you have parallel ADC data with 250 MS/s. The sampling window for the LVDS data shouldn't be smaller than at least 1 or 2 ns, so there's no actual length matching problem with 15 cm trace length (about 1 ns total propagation delay). I presume that you have receiver side 100 ohms termination, any differential trace impedance in a 70 to 150 ohm range won't actually affect the bit integrity. Crosstalk between bits might be a problem only if there's no differential routing at all.
 

SamV

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All, thanks for the responses!

Yes, this is from a 12 bit parallel interface ADC.
Just in case any of you are confused by the output of the nuclear sensor I would mention that each event is detected and outputted as a grouping of 512 samples, the missing pulse in the second plot is caused by a false trigger on the noise.
FvM, thanks for pointing this out. I did a calculation using FR4 as the dielectric and calculated a wavelength of 54.7cm. With regards to FPGA timing issues, yes this is something we've considered. Prototype 2 has a larger FPGA design than prototype 1, however our collaborator has already investigated this as a source of the noise issues.
The company that is responsible for the trace routing on prototype 2 was not properly informed of the importance of the routing. Prototype 2 is actually 2 boards, one board which has some special electronics and our sensor on it and another which has the FPGA. The boards were laid out by 2 different people, the engineer responsible for the FPGA did a reasonable job routing the LVDS signals as pairs, however other PCB's routing was neglected.

Thanks for the insight all,

-Sam
 

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Yes, this is from a 12 bit parallel interface ADC.
:)

I'd check bit-9 routing on the sensor board as a suspect problem bit (you might just cut the traces and route a 50ohm twisted pair on the sensor board. I'd have to really think about which other bit(s) is having problems, but it should be easy to figure out as it has a certain consistent delta outside the bit-9 problem.
 

SamV

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Yes, bit 9 is quite suspect in the data. My boss is a scientist and wants me to look at the layout of prototype 2 to see if there is any trace-cutting, jumper putting type stuff which could be done to prove that the problem is fixable by correcting the routing.
I'll post back if anything interesting..
 

mtwieg

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If you think data corruption is an issue, I would lay out the data in binary and see if shifting any one bit forward or back by one sample cleans up the result. But at a glance I doubt that is the main problem. If anything it looks like they may have completely switched a couple bits (hence the sawtooth shape of the waveform, which can result from switching adjacent bits)...
 

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