I implement a design in spartn3, and set the io standard to lvcoms33(or lvttl) but it always fails in mapping "ERRORack:1655, the timing-driven phase encoutered an error".
if I change the io standard to lvcmos25, then it pass.
Dose anybody know what's the problem?
Thanks in advance
gauz
I implement a design in spartn3, and set the io standard to lvcoms33(or lvttl) but it always fails in mapping "ERRORack:1655, the timing-driven phase encoutered an error".
if I change the io standard to lvcmos25, then it pass.
Dose anybody know what's the problem?
Thanks in advance
gauz
The voltage thesholds for LVCMOS25 and LVCMOS33 are different. Possibly signals are failing their setup and hold times? Can you specify a slower clock before you compile?
Alternatively, are you trying to specify LVCMOS33 on a bank which does not support it?
Thanks for Pootle's reply.
I slacked the clock frequency but the same error occurs.
I leave the io location no specified and the io standard is still lvcmos33, it pass too.
it's really a puzzling bug, no more hint from ise tool but the "ERRORack:1654 - The timing-driven packing phase encountered an error."
if I uncheck the option "performing timing-driven packing and placement" then the Map stage could pass but fail in routing saying no all net are routed.
is it possible a bug from ISE?
Added after 5 hours 32 minutes:
Bug fixed, due to several no specified ports lockation which I am not finally determined.
I had thought if I don't specified the port location, the tool will automatically assign an available location to the port, but why it doesn't?