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If you review an analog IC design textbook (e.g. Razavi) you'll find criteria to determine the region when knowing Vds, Vgs and Vth. Usual SPICE simulators don't display the region (Some Cadence tools do, I believe), but could write measurement expressions that show it.
Correct, calculating Vds and Vgs knowing the threshold voltage will solve the problem. I do know that cadence display the operation region and eldo and Hspice can give region, gds, Ids, cds, cgs, and ..... in a file i forgot the extension. So does LTspice can make life easy and add some sort of configuration to get these information easily.
I'm not aware of a built-in Ltspice function for displaying the region. To evaluate the information for each transistor without node information provided by the user, the function has to be built into the transistor models. There's little chance to add it by the user. The nearest equivalent would be a wrapper subcircuit for MOS transistor with an additional pin or an internal node voltage presenting the region information.
I dont have access to cadence at this moment I need to figure out the way to extract the operating region, gm, rds and so on, do you come cross any free simulator that can do that?
Thank you for your response
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