LTspice Error: Time step too small

[munazzah]

Hello,
I'm simulating a circuit in LTspice with third party spice models aaded to it. I encountered several errors but got them solved with the help of many forums. The last error message was "Analysis: Time step too small; initial timepoint: trouble with u3:40ua-instance j:u3:12" I tried the following as it was recommended on a forum

But now I'm not getting the desired results. My circuit is shown below, it is a biasing circuit of an RF PCB which should give 50 V on "Vout" node and -5-0V regulated voltage on "Vgate". This circuit is taken from Ampleon application note AN11130. Schematic file is attached below. Any help would be highly appreciated.

Regards
Munazzah

 

[FvM]

If you want others to check your simulation circuit, add all non-standard symbols and models to the archive.

 

[munazzah]

Here they are.

 

[mtwieg]

Here they are.

Also need to include symbol files (.asy).

In general, you should minimize the use of macromodels and third party models whenever possible. Substitute behavioral sources when possible, especially for simple components like op amps and logic gates. Once the simulation is working, you can replace them with accurate models one at a time, if you wish.

Also keep in mind that the error message will often misidentify the issue. I've had many occasions where I saw the same timestep error, and referred to some node inside a macromodel, but fixed it by changing things outside the model.

 

[dick_freebird]

Behavioral and ideal sources can introduce timestep problems when their functions and derivatives are any of (unbounded, discontinuous, non-monotonic, hysteretic). The built-in models may misbehave if any capacitance values are absurdly small.

Look at things connected to the called-out nodes and elements for such suspects. They could be B sources buried inside a subcircuit model that go to infinity or divide by a zero value because you left an argument to default, etc.

 

[cupoftea]

i think this is a good place for this type of ltspice problem

LTspice groups.io Group

This group is dedicated to *LTspice*. LTspice® is a free SPICE electronic circuit simulation program. Download LTspice at http://www.analog.com/LTspice. This group is independent from the owner of LTspice (Analog Devices (ADI), formerly Linear Technology (LTC)). It is a user's group, made up...

groups.io

....mind you , the Graet guy Helmut Sennewald, who used to keep this forum, has sadly passed away..may he rest in deserved peace.

 

[mtwieg]

Behavioral and ideal sources can introduce timestep problems when their functions and derivatives are any of (unbounded, discontinuous, non-monotonic, hysteretic).

Sure, it's possible for simple behavioral models to give bad results, but such issues are generally easy to solve via common sense, and the models are transparent for debugging. On the other hand, LT's macromodels are perfect black boxes, and give zero useful guidance on how to debug them when they misbehave. For example, in this case the error message references a node inside a macromodel which cannot be observed or analyzed.

 

[d123]

Hi,

Have you tried modifying Maximum Timestep, Time to start saving data (and Stop time)? > Would modifying those parameters throw up functional simulations but that show 'false' results?
Does your simulation duration give U3 enough time to start up? > Does U3 datasheet give you any clues as to why there is 'trouble with U3'?
40u/5n is 8,000 points - does LTSpice like that for complex circuits (maybe the problem isn't U3 at all but simulation tool limitations)?
Not questions expecting any answers, just suggestions to bear in mind.

 

[cupoftea]

sometimes shovelling small caps all over the place reduces the dv/dt's, and helps it come to convergence.

 

[munazzah]

Also need to include symbol files (.asy).

I've already attached it initially in my question

 

[munazzah]

In general, you should minimize the use of macromodels and third party models whenever possible. Substitute behavioral sources when possible, especially for simple components like op amps and logic gates. Once the simulation is working, you can replace them with accurate models one at a time, if you wish.

I tried replacing LM7301 with UniversalOpamp2 but still not getting desired results, though it didn't give any error

--- Updated Aug 23, 2021 ---

Have you tried modifying Maximum Timestep, Time to start saving data (and Stop time)? > Would modifying those parameters throw up functional simulations but that show 'false' results?

Yes I tried that after your suggestion, but it didn't help. Any recommended settings for these prameters?

--- Updated Aug 23, 2021 ---

sometimes shovelling small caps all over the place reduces the dv/dt's, and helps it come to convergence.

Do you mean to add this spice directive?
.options cshunt=1e-15

I already tried that but again it didn't give the exact result, although timestep error was gone

--- Updated Aug 23, 2021 ---

In general, you should minimize the use of macromodels and third party models whenever possible. Substitute behavioral sources when possible, especially for simple components like op amps and logic gates. Once the simulation is working, you can replace them with accurate models one at a time, if you wish.

Can you please tell me how can I replace LT4256-1 and LM7301 with behavioral sources ?

 

[d123]

Hi,

If that didn't work, no idea. If reducing Stop time to e.g. 5 us or 10 us makes no difference, not sure what to suggest. Not an expert... See if LTSpice in the general settings for simulations has a maximum number of - I think they may be called - iterations, and if you can change the number. I'm guessing about that parameter, but 100 iterations (or whatever the word is to express what I mean) to cover 8,000 points might make the simulation not work. Again - I'm guessing and might be getting that concept wrong, you'd need to look into LTSpice help information. Checking if the simulation program can deal with 5ns timesteps, I assume it can, is also worth looking into. I use another simulator that either almost always works/converges and only very occasionally only works/converges when I change the settings of 'TR max iteration number' and TR maximum time step, changing time step to one much larger is usually enough for the things I look at. It's set at 10G and if needs must I change it to 100us or 1ms, for example - problem is, does that create false results?

'TR truncation error factor' was also one it was suggested to change in the tool I use when simulations weren't working.

There's also one called 'Max. number of saved TR points' - I've never touched that but it's set at 1 million.

Look at about only half of the list of analysis parameters a person can twiddle, I understand about three of them:

Another example, trying to summarize the irritating afternoon for brevity's sake, yesterday I was simulating a 10 kHz typical two-BJT relaxation oscillator and a bad but functional home-brew 10 kHz oscillator design: Besides the relax osc. needing ridiculously unrealistically small resistor values and having to e.g. make one capacitor 10nF and the other 11nF just for it to start up and simulate anything that would happen in the real world, I can simulate them for up to a few milliseconds or around 100ms at most, any longer and one supposedly 'dies' and the other shows steady DC voltage outputs from 0s onwards. Another circuit, a basic inverting charge pump at 1 kHz is happy to simulate for at least 20 seconds. Go figure. I'd need to dedicate another fun afternoon to figure out the why and hopefully square the circle(s).

Sometimes you get errors from giving something too long a name or using a symbol in a name somewhere, having too many IC components (I think somebody has already said that), and so on.

Sorry I can't be of more help.

LT or AD, whoever it is now who has a proprietary forum related to the tool, might have threads with similar problems and suggestions.

 

[mtwieg]

I've already attached it initially in my question

No, you included the netlist file (.asc) and a few files with models and subcircuits in them (.lib and .txt). But the subcircuits also need symbols, which are kept in symbol files (.asy).

When opening the .asc file, the following popup appears:

And the schematic looks like this:

So it's missing the symbols for many subcircuits. Inspecting the .asc file shows where all those files should be on your machine:

SYMBOL sym\\ValVol\\TI\\LM7301 32 1168 R0
SYMBOL pot_ -432 1552 R180
SYMBOL sym\\ZZZ\\BJT\\BC857BS 272 1536 R0
SYMBOL AutoGenerated\\BSH103 -288 -48 R180
SYMBOL AutoGenerated\\BAW56_INF 464 592 R0
SYMBOL AutoGenerated\\BSS84 -784 896 M0
SYMBOL sym\\ZZZ\\switch\\SPST_ -480 -96 R0

So you need to retrieve those .asy files as well.

Also, you provided the file "LM7321.lib" but your design refers to "LM7301.lib". Need to provide the correct .lib file as well.

--- Updated Aug 24, 2021 ---

I tried replacing LM7301 with UniversalOpamp2 but still not getting desired results, though it didn't give any error

Can you please tell me how can I replace LT4256-1 and LM7301 with behavioral sources ?

Unfortunately, since I can't display your schematic properly, and the screencap of the schematic you posted above is so blurry, I can't ascertain the function of most of the components in the schematic, which is necessary to make any substitutions.

--- Updated Aug 24, 2021 ---

One other thing you can do is replace imported models with similar models built into LTspice. For example, LTspice already includes the BSS84, BC857B, and the BAW56. I'm betting the BSH103 could be substituted with the BSS123.

Here I've replaced most of the devices with built in models/symbols (except for the SPST switch, not sure what that's supposed to do). The FET connections don't seem to make any sense though. Are you sure they're right?