www.keil.com/dd/docs/datashts/philips/lpc23xx_um.pdf
Page 596
A programmable divider is included in each converter to scale this clock to the 4.5MHz (max) clock needed by the successive approximation process.
A fully accurate conversion requires 11 of these clocks.
The ARM has a crystal, the frequency of the crystal is multiplied with the pll to give the internal clk (up to 60MHz normally),
there is a peripheral clock (APB) which feeds all the peripherals, it can work at the core clock frequency or 1/2 of that or 1/4.
The ADC clock (can be 4.5MHz max) will have a clock of APB / (CLKDIV+1)
the CKLDIV is a value used by the AD to divide the clock, when it is 0 the APB is divided by 1, when it is 1 the APB is divided by 2 etc.
You can use the ADC in burst mode and enable the 4 channels you need, it will do repeated conversions starting from the lowest channel and going to the last and then redo from start.
for 10 bit accuracy the conversion takes 11 ADC clocks, 11* 4(ch) * 12000(samples)=528000Hz
this should be your ADC clock
for example with a core clock of 60MHz and APB at 1/4 (15MHz) you should set the CLKDIV to:
528000=15000000/(CLKDIV+1)
CLKDIV=(15000000/528000)-1=27.4 so use a little faster clock which is CLKDIV=27, ADC clock will be 535714Hz ,
which will result in 12.175Ksamples/channel
Alex