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Lowest mismatch variation bandgap?

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endru

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bandgap design npn

Hi,

Can anyone suggest me, which bandgap architecture that gives the lowest variation due to mismatch? Any paper? Thanks.
 

bandgap mismatch

Dear endru:

I think design and layout plan are critical points to reduce mismatch of circuit , the architecture is not a very important.

mpig
 

First of all. NPN bandgaps are always better than PNPs. If your process is bipolar or BiCMOS go for it. Now, there are several mismatch sources in a BG:

* The bipolars
* The amp
* The PMOS current mirrors
* The array of resistors

You can do now several things:

* Of course, a good layout. In general do not use minimum size devices
* Large ratio in the bipolars
* Big PMOS current mirrors. Specially large L.
* Large input pair of the amplifier. Specially large L.
* Use a unit resitor to build of your resitor values.
 

Why NPN bandgap is always better than PNP?
 

Because of the amplifier used to create the PTAT voltage.

The NPN bandgap loop is closed w/o amplifier. You have gnd->vbe->n*vbe->Rptat->gnd, so, the only error is the NPNs mismatch.

The PNP bandgap loop is closed with the amp. Then gnd->vbe->Voff_amp->n*vbe->Rptat->gnd. You also have the amplifier error.

Those errors will always be there, no matter what you do later. In one case the bipolar mismatch, in the other the bipolar mismatch + amplifier offset
 

I don't understand that:

gnd->vbe->n*vbe->Rptat->gnd

without schematic.

May be you meant process with NPN having separated collector that can be connected anywhere unlike PNP those collector always connected to P-substrate.
But it is not standard CMOS process.
 

If it is not standard CMOS process and you can create the circuit with the PNPs, the Rptat and no amplifier, then it'd be the same, just the bipolars mismatch
 

Thanks a lot guys! I agree with you.
I also found that if we stack the BJTs, the mismatch effect can be reduced. But of course with the trade-off of area..
 

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