lower power pull-up I/O

[sissi]

Hi,
i am designing pull-up I/O used in battery system. who can offer me some solutions?
thanks

 

[A.Anand Srinivasan]

it depends on the resistor or active network you use for pull up.... what r u planning on.... active network or passive network....

 

[sissi]

I used a pull-up resistor for digital I/O, so when pad is lower level, it will a larger current, and it is unadvisable for lower power chip.

 

[A.Anand Srinivasan]

it generally involves a trade off between power and speed.... if you use larger resistors your power dissipation would be low but your speed of transition would be reduced....

 

[sissi]

that is to say, if i increase the value of pull-up resistor, lower power also can obtain?

 

[A.Anand Srinivasan]

ya.... when the resistance is increased the current which is the main term in power dissipation decreases..... so power loss is reduced....