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lower power pull-up I/O

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sissi

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Hi,
i am designing pull-up I/O used in battery system. who can offer me some solutions?
thanks
 

A.Anand Srinivasan

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it depends on the resistor or active network you use for pull up.... what r u planning on.... active network or passive network....
 

sissi

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I used a pull-up resistor for digital I/O, so when pad is lower level, it will a larger current, and it is unadvisable for lower power chip.
 

A.Anand Srinivasan

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it generally involves a trade off between power and speed.... if you use larger resistors your power dissipation would be low but your speed of transition would be reduced....
 

sissi

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that is to say, if i increase the value of pull-up resistor, lower power also can obtain?
 

A.Anand Srinivasan

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ya.... when the resistance is increased the current which is the main term in power dissipation decreases..... so power loss is reduced....
 

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