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Low-voltage low-power RF design: mind struggling!!!!

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Full Member level 6
Jul 10, 2001
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Hi all,

The upcoming of very deep submicrometer CMOS technologies (0.13, 0.09, 0.065...) make that new systems must be designed for supply voltages smaller that 1.2V.

What are the implications on noise, linearity, DR, SNR, current consumption of implementing in those technologies RF systems like WLAN, Bluetooth, Zigbee (802.15.4), UWB (ultra wide band)?

Are we going toward a full software radio?

Are we ready to face those design problems?

replying to myself

hi guys,

this post was meant to create a debate about the pros, cons, tradoffs, alternative solutions, etc, etc... of designing CMOS radios (RF+BB)

For instance, reducing the supply voltage makes the output swing of a power amplifier to be quite reduced. This means that for putting a given power onto a 50ohms antenna, the swing can be high enough and damage the output transistor. Could it be possible to design reduced impedance antennas or to match a 50ohms antenna to make the PA to see a, say, 10ohms antenna?

What about the receiver chain?

Come on!!!!!! Feel free to say what you think.


That is right ! we will move soon to a full CMOS ROC (radio on a chip). It is very powerful & very difficult to design. & use OFDM in its processing.

To know the difficulties of design, a start up company made ROC at 5GHz on 2 chips. The digital part was done by 6 designers in only 6 months & the analog (RF) part was done by 8 designers in 2 years !! . Those chips actually contain a HUGE number of design creativity and tricks both in analog & digital domains. It is a big challenge indeed. :roll:

Two problems I see. Lower voltage means worsening Signal to Noise ratio. Hard to get around that one. The other problem is you need to consume higher current at lower voltage in order to develop the same amount of power. So these circuits will have to support higher current densities.
When it comes to RF amps, I'd rather have 28 volts!

ahhh there is nothing more satisfying than drinking coffee thats been sitting on your p.a for 1/2 hr too keep it hot

or the nice deep purple glow of a carbon tetrode amp ....

1.2v hum i can only think of one myself

and that is great its about time we got rid of the hungry thick headed chips and saved some vakwh ... in the form of reduced energy needs globaly

the benifits outway the extra noise

becouse the point is it is so narrow banded compaired to others

noise no longer becomes a barrier becouse it is much easier to spot freq filter using a pi ratio band pass filter
{a circle of glass with a square in the middle with a dot in the middle and a silver rim

i saw this thing years ago my old boss showed me it

lol:) and a nice piece of ?glass scalled down this thing eliminates noise



Toonafishy: you said that you'll increase current for the same power. Tha's right. But, what percentage of the total power consumed is due to the PA? What if a 50Ohm antenna is adapted by means of a transformer, so that only a, say, 10Ohm antenna is seen by the PA. Yes, more current is needed, but batteries are improving so that more energy can be stored in a given volume (or mass).

Very short channel CMOS makes possible attaining Ft's of near 100GHz. Some time ago I designed an LNA in a CMOS SOI 0.12, with ft=120GHz. Also, these technologies offer multi-threshold transistors. So, a given GVO (Vg-Vt) can be reached with a smaller Vg provided that a low Vt transistor is chosen.

Very deep sub-micron CMOS is a reality. More and more effort is made to become it into the mainstream RF technology for mass applications: BT, ZigBee, WLAN (most of it, at least). Why couldn't be possible a full CMOS GSM? I know that NF and PA constraints are quite stringents, but some CMOS (specially SOI) technoloies are showing NF of less than 0.6dB. CMOS linearity is not bad.

And, most of all, you have the most of people working on CMOS!!!

Thank you all for establishing the discussion



Start-up name


Can we know the name of the start-up you cite in your previous post?


its is not true that the power consumption stays the same with a decreasing voltage. this has been a BIG concern for manufacturers. how can you increase the chip density but not increase the power consumption?? this has recently been solved.

several new techniques can be incorporated into design of transistor (i.e. CMOS) to allow a lower voltage and a lower power consumption. this is achieved by minimizing the power dissipation losses, i.e. leakage current.

check out:
and look for topics including "terahertz" (new 90nm transistor) for more information

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Low leakage

Mr Cool,

I think that you're talking about digital design. In fact, the Terahertz technology from Intel is a "FULLY DEPLETED SOI". So, you increase the sub-threshold slope. This allows to reduce the leakage current by keeping the same Vth.

There are several techniques allowing to reduce leakage current when you work in SOI. Unfortunately, Ileak only contributes to static consumption, doesn't it?

Anyway, for systems where the power consumption is not driven by the emitted power, I strongly believe that the total power consumption of systems built in advanced CMOS will decrease.

Can anybody give advise about what happens in the receiver ADC, for instance?

See you all


Have you any further info about this “glass " filter?

@ Humungus:
- Yes, short channel CMOS give ft's as large as you said allowing working at very high frequency which is quit good for chip area, as L's & C's get smaller, but make it very bad in trying to isolate devices , either using rings or triple wells or any other methods. The power is another issue that needs a good designer to play with. Now you choose which system is good according to the number of operations it can do in second per mW power consumption.

-SOI seems very good actually in RF & Analog, as you have -for example- no substrate coupling noise (you stand on oxide) which allows a good NF as you mention. Actually, not many people work on SOI yet ( although IBM adopted it already, some of IBM servers are running on processors & DRAM's that are SOI, & the performance is good as 10 times ! The main technology now in IBM is actually SOI ) but not much of foundries plan to move to SOI very soon, so - as one of IBM guys told me: " In the incoming 10 years - if we can control many such things on SOI ( gate threshold control ...etc) , you may begin design your chip on SOI ".

- Full GSM submicron CMOS design not worth your effort. You don't pay much in your design (include your burned brain in the bill) & then got low bit rates as GSM. Even CDMA may not be a good choice. The work is now, for full CMOS RF systems, is toward OFDM (orthogonal frequency division multiplexing) & there are many schemes about “no license" open frequency band (It seems good in US, but in Europe it will be difficult). The point then will be “How to use the unlimited bandwidth? “ not " How to use the bandwidth efficiently? ".

-For the start up company, it is A-T-H-E-R-O-S (h!!p:// (It is supposed not to mention a company name - according to rules- but my point here is clear!). They do their job on 0.25um standard CMOS technology! Actually, it was surprise to me.

-PA's may not be a big problem soon, although it is not easy to make on deep sub CMOS. In the suggested coming WLAN system designs, for example, they are trying to use many techniques to use PA power efficiently like beam forming ( just focus the antenna beam to the man you want to catch your message, & no one else can take it. )This method concentrates the beam power in very narrow angel - instead of ~ 360 deg.Accompanying this, guys of antenna also are asked to make very small high- gain antennas. There are many methods are supposed to work on this issues & majority still in the labs. Most depend mainly on system level design, not the silicon level.

-Inside Rx's ADC- I don't know exactly. But I know that they employ conventional ADC methods, if ADC's at those frequencies are conventional, & left many parts of the work to the DSP to do ( this is due to the used OFDM scheme). This also imposes very hard constrains on the analog RF designer to handle out a high SNR & allow DR for the output of the ADC & input of DSP unit.

Well, life will be more funny for those poor Analog/RF designers who are asked to make their work on CMOS technology which is optimized mainly to digital designers-- Enjoy !

This article may help, espacially for offset voltage considerations...


:D Really good.


I am quite impressed at your LNA design work with SOI. So far I only hear this on papers not commercial applications.

Is there any special consideration that needs to be aware of for SOI compared to standard CMOS?

If you don't mind, what was for frequency of operation of circuit with your 100GHz Ft.

What model do you use for modeling SOI. Is it BSIM SOI on @DS.

I will start my mixer design on SOI in a few months time.



I cannot give all the details of what you have to account for in an SOI LNA, but let's say that SOI is kind of super-CMOS: enhanced current drive, higher ft at same technological mode and substrate isolation. As negative points, you have to deal with all SOI issues (sorry I cannot give you details).

The specs were: inductively degenerated cascode, NF=2dB, Id~1mA, Vdd=1.2V, G~20dB, 2.45GHz. It was a first design so I cannot provide IP3 and as we were VERY bussy with other design I hadn't had time to make actual characterization.

What kind of mixer are you going to design? What technology? What freq?

How much experience do you have in CMOS rf? Are you in EU, USA, elsewhere? Looking for a job;-)?

See you



Thank you for the insights.

I don't really have that much experience in CMOS RF.

Had designed one quadrature modulator for my master thesis and will work on SOI mixer for upcoming pHD project. The specs of mixer would be for W-CDMA application with Gilbert cell topology with some variation.

I am located in Asia and not really looking for a job at the moment. Where is your location?

Do you know any good reference books for RF-SOI design



A book explainig RF-SOI??!!! Unfortunately what you're asking for doesn't exist:-( Anyway, there is a university that has worked a lot on technology characterization at RF and MW (they demontrated the feasibility of FD-SOI. Get a look at and

I don't know the specs for W-CDMA, but why not using a passive 4-transitor CMOS mixer. It has excellent linearity but relatively poor NF.

What SOI technology are you targeting? At least can we know the feature length? How many metals? Fully or partially depleted? You're in Asia, so you could be using OKI or NTT, isn't it?


Hi Humungus,

Thank you for the link.

It will be a partially depleted technology in the range of 0.18-0.25 micron length. Haven't really decided on this as I am still talking to a few foundry. OKI and NTT is among the few that will talk to too.

Which foundry do you use for your design (if that is not confidential)? There is a French SOI foundry coming in the picture late last year.

What RFIC simulator do you use for your design?

SOI links


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