Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Low speed Clock and Data Recovery

Status
Not open for further replies.

timedate

Member level 5
Joined
Jun 20, 2010
Messages
81
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
germany
Activity points
1,952
Hi, all

I am designing a optical receiver with 2 Mbps.

However, I could not find an Clock and data recovery (CDR) in that speed, and also CDR consumes a lot of power.

Therefore, I am trying to find a clocked comparator to perform the function of the CDR, since the continues comparator will change the duty cycle of my output.

So, the question is
1 Is there some low power and low speed CDR in the market?
2 Should a clocked comparator work? (a comparator with latch?) where can I find it ?

I put my design in the attached, you can find that the continues comparator changes the duty cycle of the signal.

Thanks all
 

Attachments

  • slcm001.zip
    15.7 KB · Views: 56

Hi,

maybe it is possible to transmit UART styte. Then no clock recovery is needed, but known and fix baudrate.
Or transmit like IRDA ...

Klaus
 

Is it expecting too much if we ask for a readable document describing your problem?
 

have not played with this stuff for a while, but i remember doubling the data in frequency, and the clock was easily found then.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top