Low power VLSI design techniques

blaze1200 · Dec 14, 2010

Hi,

My research is about low power design techniques.

-> Is it possible to use clock gating for DMA (asyn) ?
-> Other possible techniques besides clock gating ? (Preferably architecture/RTL)
-> Where can I obtain other testcase ? (> 10k gates + sync design)

Please advice. Advance thanks...

balavinayagam · Dec 15, 2010

hi ,
Refer this book 'Low Power Methodology Mnaual For SoC design ' by Michael keating

blaze1200 · Dec 15, 2010

Hi Mr. Bala,

Thanks for the input. :smile:

kumar781 · Jul 5, 2012

hi do you what are the recent trends in low power cmos vlsi design ...........

and what vlsi copmpanies require if we choose a project reg low power vlsi design

Low power VLSI design techniques

blaze1200

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balavinayagam

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laxman dayadi

blaze1200

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kumar781

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Low power VLSI design techniques

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