Low power VLSI design techniques

[blaze1200]

Hi,

My research is about low power design techniques.

-> Is it possible to use clock gating for DMA (asyn) ?
-> Other possible techniques besides clock gating ? (Preferably architecture/RTL)
-> Where can I obtain other testcase ? (> 10k gates + sync design)

Please advice. Advance thanks...

 

[balavinayagam]

hi ,
Refer this book 'Low Power Methodology Mnaual For SoC design ' by Michael keating

 

[blaze1200]

Hi Mr. Bala,

Thanks for the input. :smile:

 

[kumar781]

hi do you what are the recent trends in low power cmos vlsi design ...........

and what vlsi copmpanies require if we choose a project reg low power vlsi design