Low Power Design for Pseudo-Random number generator Using LFSR

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abonic

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Hi Guys.
Recently, I'm getting interested in the PRN Generator Using Linear Feedback Shifting Register(LFSR).
If Low Power Performance is desired, which Logic Type and clock strategy are preferred.
 

This is no different to any other logic question. The power required will depend on the speed and logic family used. Faster clock speed will increase power consumption and CMOS is probably the most power efficient logic family to use but may not manage the speeds you require. You can even do it in software on a simple microcontroller if the speed and power suits your needs.

Brian.
 
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