In RTL there is no low power specific gates (such as power gates, isolation/retention cells etc) available. But power aware simulators are able to understand the missing hardware components after reading power intent file and include 'virtual' cells in place of 'expected' hardware. To make it more clear, say you have specified a isolation to inputs of domain A in your UPF but as isolation cells be inserted only after synthesis, 'power aware 'simulators includes virtual cells in simulation which can act as real hardware.
Isolation cells are inserted in synth.
power gates in layout.
Even before UPF/CPF came into mainstream low power designs were made. In those days(even now in some projects) these low power cells are coded in rtl or inserted during synth/lay stages.
I used to add isolation cells in rtl few years back.
Hope this helps.