[SOLVED] low pass filter in verilog

[mazhariqbal]

Hi All,
I need some help in verilog .... as I'm new to verilog and I'm supposed to design low pass filter (order 5) ....in my case data_in is 8 bit and I want 8' bit output...... for this I want some saturation and rounding off .....it is not working properly can anyone explain this concept to me please....and I'm also confused about co efficient representation in my code as my coefficient are all less than 1....... and I'm not sure I've defined them correctly for example if one value is (-0.042138198454649167).... 10101001..can anyone tell me if this is correct????? please do reply as soon as possible...I've used coefficient in my code as parameter [7:0] b1 = 8'b10101001......

 

[FvM]

Designing a 5th order filter with only 8 bit data width seems pretty meaningless, but may be O.K. as an exercise. Assuming you want to keep at least the 8 bit resolution in the filter output most likely implies higher internal resolution and possibly higher coefficients resolution.

In any case, it's more a DSP numerical than particularly a Verilog problem. You can design the signal flow with number representation of all variables and constants by pencil and paper method and finally implement it in Verilog.

If you want to discuss specific questions, you should tell some design details first.

 

[mazhariqbal]

Yes, it is for exercise..... I've already done paper work but that is not helping much I'm posting my code you can check and tell me what is wrong with that ....here is my code .....I'm testing my filter by sine wave....but Matlab filter command gives me different result and my filter gives me different I don't know why ......

module FIR_Lowpass (Data_out, DataVal ,Data_in, Data_in_Val,clock, reset);

parameter signed [7:0] b1 = 8'b10101001;
parameter signed[7:0] b2 = 8'b00101001;
parameter signed[7:0] b3 = 8'b01100001;
parameter signed[7:0] b4 = 8'b01100001;
parameter signed[7:0] b5 = 8'b00101001;
parameter signed[7:0] b6 = 8'b10101001;

output [7: 0] Data_out;
output DataVal;
input [7: 0] Data_in;
input Data_in_Val;
input clock,reset;

reg [7:0] D1,D2,D3,D4,D5;
reg DataVal;
wire [15:0] P1,P2,P3,P4,P5,P6;

wire [17:0] Add1,Add2,Add3,Add4,Add5;
reg Val1,Val2,Val3,Val4,Val5;

always @ (posedge clock) begin
if (reset == 1) begin
D1 <= 8'h00;
D2 <= 8'h00;
D3 <= 8'h00;
D4 <= 8'h00;
D5 <= 8'h00;
end
else if (Data_in_Val)begin
D1 <= Data_in;
D2 <= D1;
D3 <= D2;
D4 <= D3;
D5 <= D4;
end
end

always @ (posedge clock) begin
if (reset == 1)
Val1 <= 1'b0;
else if (Data_in)
Val1 <= 1'b1;
end

always @ (posedge clock) begin
if (reset == 1)
Val2 <= 1'b0;
else
Val2 <= Val1;
end
always @ (posedge clock)begin
if (reset == 1)
Val3 <= 1'b0;
else
Val3 <= Val2;
end
always @ (posedge clock)begin
if (reset == 1)
Val4 <= 1'b0;
else
Val4 <= Val3;
end
always @ (posedge clock)begin
if (reset == 1)
Val5 <= 1'b0;
else
Val5 <= Val4;
end
always @ (posedge clock) begin
if (reset == 1)
DataVal <= 1'b0;
else
DataVal <= Val5;
end


assign P1 = Data_in * b1;
assign P2 = D1 * b2;
assign P3 = D2 * b3;
assign P4 = D3 * b4;
assign P5 = D4 * b5;
assign P6 = D5 * b6;

assign Add1 = P1 + P2;
assign Add2 = P2 + P3;
assign Add3 = P3 + P4;
assign Add4 = P4 + P5;
assign Add5 = P5 + P6;

assign Data_out=Add5[17:10];/////???????????? here is problem how can I get accurate 8,Bit data out

endmodule
/////
my question is how can I make data out accurate 8'bit..... plzz help me

 

[FvM]

- Your filter signals and coeffciients are unsigned by Verilog default. Is this what you want?
- When adding two numbers, no automatic bit width extension is performed
- Your output signal is only formed by the two last stages. The others are ignored.
- How did you calculate the coefficient scaling?

 

[shaidi]

hi brother thanks for sharing a nice and helpful code.can you send me code for high pass filter in verilog.i shall be very thankful to you for this act of kindness.

Yes, it is for exercise..... I've already done paper work but that is not helping much I'm posting my code you can check and tell me what is wrong with that ....here is my code .....I'm testing my filter by sine wave....but Matlab filter command gives me different result and my filter gives me different I don't know why ......

module FIR_Lowpass (Data_out, DataVal ,Data_in, Data_in_Val,clock, reset);

parameter signed [7:0] b1 = 8'b10101001;
parameter signed[7:0] b2 = 8'b00101001;
parameter signed[7:0] b3 = 8'b01100001;
parameter signed[7:0] b4 = 8'b01100001;
parameter signed[7:0] b5 = 8'b00101001;
parameter signed[7:0] b6 = 8'b10101001;

output [7: 0] Data_out;
output DataVal;
input [7: 0] Data_in;
input Data_in_Val;
input clock,reset;

reg [7:0] D1,D2,D3,D4,D5;
reg DataVal;
wire [15:0] P1,P2,P3,P4,P5,P6;

wire [17:0] Add1,Add2,Add3,Add4,Add5;
reg Val1,Val2,Val3,Val4,Val5;

always @ (posedge clock) begin
if (reset == 1) begin
D1 <= 8'h00;
D2 <= 8'h00;
D3 <= 8'h00;
D4 <= 8'h00;
D5 <= 8'h00;
end
else if (Data_in_Val)begin
D1 <= Data_in;
D2 <= D1;
D3 <= D2;
D4 <= D3;
D5 <= D4;
end
end

always @ (posedge clock) begin
if (reset == 1)
Val1 <= 1'b0;
else if (Data_in)
Val1 <= 1'b1;
end

always @ (posedge clock) begin
if (reset == 1)
Val2 <= 1'b0;
else
Val2 <= Val1;
end
always @ (posedge clock)begin
if (reset == 1)
Val3 <= 1'b0;
else
Val3 <= Val2;
end
always @ (posedge clock)begin
if (reset == 1)
Val4 <= 1'b0;
else
Val4 <= Val3;
end
always @ (posedge clock)begin
if (reset == 1)
Val5 <= 1'b0;
else
Val5 <= Val4;
end
always @ (posedge clock) begin
if (reset == 1)
DataVal <= 1'b0;
else
DataVal <= Val5;
end


assign P1 = Data_in * b1;
assign P2 = D1 * b2;
assign P3 = D2 * b3;
assign P4 = D3 * b4;
assign P5 = D4 * b5;
assign P6 = D5 * b6;

assign Add1 = P1 + P2;
assign Add2 = P2 + P3;
assign Add3 = P3 + P4;
assign Add4 = P4 + P5;
assign Add5 = P5 + P6;

assign Data_out=Add5[17:10];/////???????????? here is problem how can I get accurate 8,Bit data out

endmodule
/////
my question is how can I make data out accurate 8'bit..... plzz help me