Low noise PWM demodulation

[Archimedes]

I have a CMOS gate that outputs a PWM signal at 32 MHz, 3.3V and I use an active filter to integrate it into the audio signal. The problem is that the duty cycle change is only a few percents and I need a low-noise signal while keeping power consumption low enough (can't afford more than 0.4-0.5 mW for this). The only solution I came up with is to increase PWM amplitude (there's a 12V rail in the circuit I can use for this) but the frequency and amplitude are too high for conventional level shifting circuits. Op amps and comparators are not suitable for this too since they consume too much power. I also saw some RF circuits with step-up transformers used for signal amplitude amplification, but they all have 50 Ohm input impedance, that's too low.
So what is the best way to get a low-noise signal?

 

[FvM]

To reproduce the problem, we need to know about audio frequency range and target signal-to-noise ratio.

 

[Archimedes]

Frequency range is 70-1400 Hz, target SNR is at least 80 dB, higher is better. I use MCP6401 op amp for active filtering, it has 28 nV/√Hz noise density, total filter noise over specified bandwidth is 3.9 μV, filter gain is 2.

 

[KlausST]

Hi,

If you need low power....I'd go for a passive filter.

The problem is that the duty cycle change is only a few percents

So this means that there is a (large) DC value added with a small AC (audio).

I don't see a reason why this is. If you want good SNR ... you usually make the signal large on the PWM side and divide it down at the analog side. While dividing down the analog signal you also divide down the noise .. resulting in better total SNR.

Klaus

 

[frankrose]

Dot you have some spare at the PWM side? Can't you gain the signal digitally?

 

[dick_freebird]

Seems like you need to put gain before the PWM so that
at max input signal you get min-to-max duty cycle. SNR
numerator sounds like the problem.

 

[Archimedes]

I'd go for a passive filter.

I'd go too as if the signal amplitude was high enough.

So this means that there is a (large) DC value added with a small AC (audio).

Right, and raising PWM amplitude increases not only the DC value but also the AC part, isn't it? And with much lower added noise.

make the signal large on the PWM side

Dot you have some spare at the PWM side?

Seems like you need to put gain before the PWM

The signal is coming from a sensor as a phase difference between two square waves and I'm using a XOR gate to measure it. I don't see any ways to add gain at PWM stage.

Can't you gain the signal digitally?

The signal is sampled by 24 bit ADC of MSP430AFE253 and it's still not enough for digital gain.

 

[crutschow]

Use a stage or two of passive filtering to get rid of most of the high frequency carrier, then an op amp active filter with gain.
2% duty-cycle with a 3.3V signal will give an analog output of about 66mV.
A gain of 15 will convert that to a 1V audio signal.

For low noise, the noise in the power to the 3.3V PWM circuit will need to be very low (no more than 6.6uV total in your audio frequencies of interest of 70Hz-1400Hz for a 80dB or better signal S/N).
You can likely do that with a large RC time-constant filter in the power to the circuit.

 

[dick_freebird]

You may need to oversample (average) quite a bit, if you
are based on a trivial phase difference that is near the
baseline jitter then there's not much you can do except
call out the average.

Perhaps the phase sensitivity of the sensor can be
increased somehow (delta phase per delta whatever).
Geometry? If this is like a LVDT or inductive angle
sensor, maybe a lever arm is your gain medium?

I have not seen so far, anything about "the big end".
If you're only using / caring about (say) -5% to +5%
of full scale then there's been a mistake in selecting
or setting up the sensor relative to the sensed
quantity and its range.

 

[dick_freebird]

It seems to me that you really want a time-to-digital
converter (or phase-to-digital, but if you have fixed
frequency excitation then what't the diff?) and are
going at it in a very roundabout way. Choosing to use
an XOR gate and RC filter rather than a purpose-built
phase detector IC, why?

 

[KlausST]

Hi,

I'd go too as if the signal amplitude was high enough.

I don't understand this statement.
What has the signal amplitude to do with active or passive filters.
I agree with crutschow: passive filtering, at lease second order, then amplifying.
Another benefit may be - if possible - to synchronize the sampling rate to the pwm frequency (or an integer division of it)

Klaus

 

[frankrose]

The signal is sampled by 24 bit ADC of MSP430AFE253 and it's still not enough for digital gain.

And are you using some averaging after the ADC? Any digital filtering?

 

[Archimedes]

It seems to me that you really want a time-to-digital converter

All converters I found don't have sufficient resolution or/and sampling frequency.

Choosing to use an XOR gate and RC filter rather than a purpose-built phase detector IC, why?

I've searched a lot and I haven't found anything more suitable than XOR gate, can you please advise some good phase detector ICs?

You may need to oversample (average) quite a bit

Another benefit may be - if possible - to synchronize the sampling rate to the pwm frequency (or an integer division of it)

Great advises, I'll try that.

I don't understand this statement.
What has the signal amplitude to do with active or passive filters.

I mean, PWM amplitude. If it's high enough then the AC component will be larger after integration and amplification might not be needed.

 

[FvM]

Did you check if the jitter of the 32 MHz signal is low enough to actually achieve the intended SNR? 80 dB with only a few percent PWM refers to a 100 fs order of magnitude. Not very realistic in digital logic implementation.

 

[Archimedes]

Oh, right.. I guess I need to find ways to reduce the frequency.