Low COST Xilinx FPGA evaluation boards somewhere??

burched fpga 300

Problem is always we don't find correct packages..., seem always the chip package is the smallest available ie Spartan II XC100 with a PQ208 package, this reduce the user IO blocks available count dramatically

it's easy to find AVNET boards, or INSIGHT boards. BUt it might be possible to find some more little companies who are targetting low cost education stuff like boards.

Any help appreciated

With regards

moZfet,

I don't really know the price range you had in mind, but a friend of mine just purchased on the these. He had a few good things to say about it.

Although it is contrained to 208 pins, it is a spartan 2e 300, Just a little bigger than the 100.

hxxp://w*w.burched.com.au/

Hope this helps a little.

robotman

It's interesting.
Thanks.

robotman said:

moZfet,

I don't really know the price range you had in mind, but a friend of mine just purchased on the these. He had a few good things to say about it.

Although it is contrained to 208 pins, it is a spartan 2e 300, Just a little bigger than the 100.

hxxp://w*w.burched.com.au/

Hope this helps a little.

robotman

Click to expand...

sadelly it's PQ208, for exemple if u try to place & route the oregano systems 8051 core, u will get an error while starting place & route

this is because this oregano core might require 155 ext io blocks ( that I still find wierd ) url. h**p://www.oregano.at/services/mc8051/mc8051_design.zip:

Spartan-IIE User I/O Chart
XC2S300E:
max I/O = 329
pq208 I/O = 146
ft256 I/O = 182
fg456 I/O = 329


as u can see for same device samellest package reduce for the half available IO blocks

But the board url u sent is just so nice, unfortunately it's not ft256 or fg456

With Regards,

moZfet

Hi mozfet!

Oregano's design needs so many I/O's because they have separated the busses. I think there are seperate busses for XDATA and CODE. And the I/O ports are not bidirectional. Every 8bit port consists of 16 lines, 8 for input and 8 for ouput. I had the same problem while fitting their 8051 to XC2S200 with PQ208! Theses busses are designed to connect to FPGA internal peripherals. You don't need to lead all of them to external pins.

regards
The General

GeneralMadDog said:

Hi mozfet!

Oregano's design needs so many I/O's because they have separated the busses. I think there are seperate busses for XDATA and CODE. And the I/O ports are not bidirectional. Every 8bit port consists of 16 lines, 8 for input and 8 for ouput. I had the same problem while fitting their 8051 to XC2S200 with PQ208! Theses busses are designed to connect to FPGA internal peripherals. You don't need to lead all of them to external pins.

regards
The General

Click to expand...

ya even worse, I know now that this core is orignally designed for be a block in a SoC design

Regards