loop with even and odd input

[fanwel]

Hi all,

I try to write a code that will differentiate the input either odd or even for obtain the output.
Below is my code:
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package my_data_types is
type vector is array (natural range <>) of integer;
end my_data_types;

library ieee;
use ieee.all;
use work.my_data_types.all;

entity even_odd is
port (clk: in bit;
A: in vector (7 downto 0);
out_odd: out vector (3 downto 0);
out_even: out vector (3 downto 0));
end even_odd;

architecture even_odd of even_odd is
begin
process(clk)
begin
if (clk'event and clk='1') then
for i in 7 downto 0 loop

out_odd <= A(2*i);
--A((2*i)+1);

out_even <= A(2*i-1);
--A((2*i-1)+1);

end loop;
end if;
end process;
end even_odd;
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But then, there is an error occurred when I compile the code.
Error (10381): VHDL Type Mismatch error at even_odd.vhd(23): indexed name returns a value whose type does not match "vector", the type of the target expression.

Can anyone help me..where my mistake? Many thanks

 

[TrickyDicky]

the statement A(2*i) (and the -1 version) only return a single bit. But out_odd and out_even are 4 bits long each. I think you meant this:

for i in 3 downto 0 loop  --only 3 downto 0 otherwise you go out of the range of A with i*2
  out_odd(i) <= A(i*2+1);
  out_even(i) <= A(i*2);
end loop;

 

[fanwel]

Hi TrickyDicky,

Sorry, Im not clear with:

for i in 3 downto 0 loop -- it's will only read the input from that range only? Although my input is in range 7 downto 0.

Thanks for reply

 

[TrickyDicky]

yes, but if you look at the code, it will access all 8 bits.

3*2 +1 = 7
3*2 = 6
2*2 + 1 = 5

etc
If you kept it like you did before, it would try and access bit 15 downto 0, and bits 8 to 15 dont exist, so you would get a bad index error.

You are only connecting 4 bits for each output, so you only need to have 4 iterations.

 

[fanwel]

Hi TrickyDicky,

Okay, i understand now..many thanks for helping me.