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looking for Verilog to VHDL translator

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neocool

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verilog to vhdl translator

Hi,
I was looking on internet for Verilog to VHDL translator and found the only free link which does not work:
URL: ftp://ic.berkeley.edu/pub/Tools/verilog2vhdl.tar.Z

Also, there's commercial X-HDL, but I it does not allow to copy and paste the translated VHDL resulting code.

Is there anything else for free or some evaluation copy to translate about 15 Verilog files?

Thanks
 

free verilog to vhdl translator

of course X-HDL can do, if you have a license.
 

verilog2vhdl.tar.z

You can download X-hdl for evaluation .. This is THE BEST TOOL .the rest are just toys .. X-hdl . will convert a sinthetizable vhdl or verilog on a
sinthesizable core in verilog or vhdl ..
Is the best!
 

verilog to vhdl translator + free download

In options:
You should change output options from "windows" to "file".
 

verilog to vhdl translation

eltonjohn said:
You can download X-hdl for evaluation .. This is THE BEST TOOL .the rest are just toys .. X-hdl . will convert a sinthetizable vhdl or verilog on a
sinthesizable core in verilog or vhdl ..
Is the best!

Have you ever try X-HDL before?
Is the verilog translate from VHDL save?
Should we check it out with all the bench?
 

verilog vhdl translate

jamesyang1209 said:
In options:
You should change output options from "windows" to "file".

Hmm, will try that one,
Why would they allow it though if window is not permitted..
another nice trick ? :)


h**p://www.ocean-logic.com/pub/vhd2vl.tgz
That one is VHDL to Verilog only, right?
 

free download of xhdl converter

neocool said:
jamesyang1209 said:
In options:
You should change output options from "windows" to "file".

Hmm, will try that one,
Why would they allow it though if window is not permitted..
another nice trick ? :)


h**p://www.ocean-logic.com/pub/vhd2vl.tgz
That one is VHDL to Verilog only, right?

It's only a toy.
X-HDL is much better.
 

hdl translator

According to my personal exp. I will info people who would like to use x-hdl that you still have to make some modification on the code and simulate it after you done the tranx job. :eek:
 

free verilog vhdl translator

bravobravo said:
According to my personal exp. I will info people who would like to use x-hdl that you still have to make some modification on the code and simulate it after you done the tranx job. :eek:

You have use X-HDL. Good.
Is the result fine?
If all the codes are only one clock source and are all FlipFlop (no latch), should I need to modify the results?
 

SynaptiCAD has a Verilog to VHDL translation tool that can be found at https://www.syncad.com/hdl_translators.htm . It is not free, but they have 1-day leasing that you can purchase. They also provide translation services for those that don't want to learn all the differences in the languages.
 

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