Looking for Verilog source code for E1 to Ethernet mapper

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Laplace

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ethernet mapper

I am designing an FPGA takes E1 signals and maps them into the ethernet frames.

It will be functioning like MAC chips.

Has anyone got related source code (Verilog) and/or suggestions?

Thanks,
Laplace
 

Hi

This subject was discused in previously. See :

**broken link removed**

Maybe you will find some info or some interesting links.
 

It seemed it is so hot technology!But I don't think it is difficult to implement.
E1 interface + ethernet interface + cache controller, nothing can defeat us.
 

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