I want to use Alliance CAD.
I have the VHDL code(say)
Please tell me the steps (commands) for,
Simulation
Synthesis
Place and Route
Layout(Real) generation
I have done the above things using the MakeFile supplied with the alliance>tutorials
for that tutorial design, but now I want to do my own VHDL design.
I don't think you can use verilog with alliance cad tools. You can use some other verilog simulation software like icarus verilog simulator which is free.
If you do get a good tutorial for alliance cad tools please do let me know as well
Hi i am using alliance cad tool. I have a problem when i run s2r command and look at the cif file generated. It is generating nwell for vss as well and the poly even if it is an n channel device. any solution how to verify it. Im using the alliance version of alliance-5.0-20090901-i386-sl5soc.i386.tar.gz