Looking for materials on die size estimation in digital core

[ne.me.sis]

die size estimation

Please share your experience on die size estimation in digital core.
If you have the design spec, no hardware in mind, how would you start?

 

[eda_wiz]

die size estimation

try this free tool
https://www.chipestimate.com/

 

[abhi_123]

die size estimation

Let Total Cell Area be ‘X’ (which is known to us)
Let Total Core Area be ‘Y’
Now Decide upon the Final Utilization of Core area You want, say 85 %
To leave margin for Routing Resources and other optimization, take Utilization as 65% - 75 %
Now X = 0.75 * Y
So Y can be calculated

 

[jjww110]

die size estimation

i think first to determine core limted or pad limted!!

 

[odeafeiner]

Re: die size estimation

yes.

It will be different between pad-limited and core limited.

And if you use UMC technology, i remember that they
have such tools in the web also.

 

[papertiger]

die size estimation

find a similar product and estimate the die size.

 

[ne.me.sis]

Re: die size estimation

Thanks for all the inputs. But let me make the problem simple.

It is an existing chip. We are adding in some additional hardware in the digital core. If you want to estimate how much increment in gate count(which I can convert to die size later) at the very beginning, before you have your RTL ready. How would you start?

 

[zyphor]

Re: die size estimation

I think you should have knowledge on :
1. gate counts of the design
2. Memory size
3. I/O
4. Power ring
5. Power strap

and (1+2+3+4+5)/70%= rough die size

 

[aifi]

Re: die size estimation

hi..

as for me, i use PKS to estimate the die size, create initial floorplan in PKS and you will mesure the width and hight for the core after initial placement in PKS..

correct me if i go wrong..