I need information regarding specification of manufacturing process (standard cell libraries).
I designed a digital core, and i need to estimate how much power will it take and what would be the size.
i know that a rough estimation use NAND2 specification for example uW/MHz and cell size.
another estimation is how many Kgates in mm2.
Where can i get such info for example for 65 nm LP (any vendor will do- just an estimation)
1) can you be clearer of what u are looking for ....u mean the spec of your process?? it should be available in the ome/PWD directory...
2) for size you can use layout techniques, power can be from a simulation. In an advanced level you have variety of options to build a test bench and estimate it...
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olease rephrase your question once again to understand it even better,,,,,