Looking for information/VHDL core to determine yaw angle from a gyroscope

[kureigu]

Hey all, I'm trying to write some VHDL to determine the angular change of a gyroscope on one axis.

I've got as far as writing a very simple linear integration component to output an angle (in hex) to a 7-seg display, but I'm still facing the age old issue of gyroscopic drift. There is slight noise on the output of my gyro, which makes it hard to get a consistent 'at rest' value to minimize the drift that way. However, I need to maintain an accuracy of ~0.2deg and I'm afraid if I high-pass filter the output I'll lose some accuracy in my reading.

Does anyone know of a VHDL core that could potentially save me a lot of time and difficulty? I'm also open to any theory, papers or other information people may know of that could help me out here.

Any helpful advice is much appreciated!

 

[TrickyDicky]

This is not really a VHDL problem, more of an algorithm problem. You probably need to model the system in something like matlab and see what kind of error you can cope with.

 

[kureigu]

The part about looking for a core is a VHDL problem. But yes, I realise on the whole it's maybe more of a DSP issue.

I was hoping for a response from a VHDL/FPGA standpoint though, because if I asked in a DSP forum I'd get responses with algorithms that might be easy enough to implement in C, but difficult to sythesize from VHDL in hardware.

 

[TrickyDicky]

If someone just handed you a VHDL core, wheres the challenge in that?
I get the feeling gyroscope control is a little more specialised than other applications, hency why there are fewer cores around, and they probably dont do what you want. Have a poke around opencores.org but most of whats there are standard interface implentations and video or audio DSP cores.

 

[kureigu]

Yeah, I just wondered since gyroscope drift is a pretty persistent problem if by any chance anyone here might have dealt with it before.
And I wasn't purely looking for a core, I did ask if anyone could point me towards any info on dealing with it in FPGAs or had any general advice.
Thanks anyway, though.