Hi prakash timing analysis can be done to verfiy whether we are meating thse stup time and hold time values.
The main interfaces for the timing analysis are
1.Common clocking:in this a seperate clock is used to drive both the driver and the receiver.exm:all the SDRAM interfaces are this type.
2.Source synchronous iterfaces:in this driver is used to send the both clock and the data siganls.Exm:ddr interfces.
i am attaching the equations for calculating the setup and hold margins