Looking for a clock that activates after 10ns

i need a clk that only will activate after 10ns....any idea on how can i do it?

0 for 10ns....then will start clockin after 10ns......

anybody knows?

Re: vhdl testbench help

Declare a signal which will stop clock.
Activate this sigal after 10 ns.
For example:

signal stop_clk : std_logic := '0';


stop_clk <= '1' after 10ns

clock_final <= clock and stop_clk;

Hope it helps,
Kr,
Avi
http://www.vlsiip.com

vhdl testbench help

In fact;
Declare a signal S initiated to 0
S<='1' after 10 ns;
process (S)
clk<='0';
wait for X ns;
clk<='1';
wait for X ns;
end process;

Re: vhdl testbench help

Dear mouzid,
I think your solution unfortunately, on this occasion isn't going to work, because the process is sensitive to S, and S does NOT change once it has changed at 10ns.
And why complicate things, when it can be done in such a simple way.
Kr,
Avi
http://www.vlsiip.com

vhdl testbench help

Hi Avi,
I mensionned to in my solution to initiate S to zero so it will change after 10 ns.
Thanks.

Re: vhdl testbench help

haha...alrite....thanks alot to both of u...i manage to get it worked already..=D

vhdl testbench help

Hello all,
@mouzid & cloudz88
That told you Avimit is true since the process will generate only one clock pulse after 10 ns. I think you meant to write:

S<='1' after 10 ns;
process
wait until S='1';
clk<='0';
wait for X ns;
clk<='1';
wait for X ns;

@ Avimit
What do you think about this solution ?
The technique you provided is a kind of gating technique of the clock. I is alright but in certain application it doesn't. In fact, when the enabling stop_clk signal comes in an appropriate time (when clk is low) that's ok. Now, Suppose that stop_clk rises when clk is high. As a result the width of the first pulse will be inferior than the conventional half period of the clock cycle and this can cause the disfonctionnement of the system.

Cheers,
Master_PicEngineer.

Re: vhdl testbench help

Dear Master_PicEngineer,
We are talking about testbenches. You are talking about clock gating. These two are different things. Here you know that your stop signal will go 0->1 only once. Here we are not using any kind of conditional gating for the clock. So this is different from the concept of 'clock gating'.
I gave a solution of what was asked, and I still belive its a working soultion.
Kr,
Avi
http:/www.vlsiip.com

vhdl testbench help

I totaly agree with you Avimit.
Cheers,
Master_Pic_Engineer