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I think your solution unfortunately, on this occasion isn't going to work, because the process is sensitive to S, and S does NOT change once it has changed at 10ns.
And why complicate things, when it can be done in such a simple way.
@mouzid & cloudz88
That told you Avimit is true since the process will generate only one clock pulse after 10 ns. I think you meant to write:
S<='1' after 10 ns;
wait until S='1';
wait for X ns;
wait for X ns;
What do you think about this solution ?
The technique you provided is a kind of gating technique of the clock. I is alright but in certain application it doesn't. In fact, when the enabling stop_clk signal comes in an appropriate time (when clk is low) that's ok. Now, Suppose that stop_clk rises when clk is high. As a result the width of the first pulse will be inferior than the conventional half period of the clock cycle and this can cause the disfonctionnement of the system.
We are talking about testbenches. You are talking about clock gating. These two are different things. Here you know that your stop signal will go 0->1 only once. Here we are not using any kind of conditional gating for the clock. So this is different from the concept of 'clock gating'.
I gave a solution of what was asked, and I still belive its a working soultion.