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Look up table for sine wave generation

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Vijay Vinay

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Friends,
I am a final year student pursuing ECE. I am currently working with Mission 10x kit through which I am interfacing FPGA programming. I have to generate a sine wave so that I can collect my o/p through DAC . I have generated the sine wave values for one cycle but I have no idea how to generate a look up table so that I can implement the values for generating the sine wave. Please help me friends. Its urgent. I will be happy if my problem gets rectified at the earnest......

Thanks,
Vijay Vinay
 

Vijay Vinay

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Thank you andre_teprom for your valuable information.... but I have generated the values for my sine wave... I dont know how to insert the txt file in my verilog code... Please help me....Its urgent.............



Thanks,
Vijay Vinay
 

dpaul81

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Hi,
I had used this in an internship project for sine wave generation and was very successful. No need of implementing look-up table and stuff!
You can generate a sine wave using Maclaurin series equation and using up to only 3 terms in the equation. The maximum error percentage between an actual sine function and the Maclaurin representation (using 3 terms) is 0.99%.

You can implement in VHDL/Verilog the following equation to get as output a sine wave:
Code:
f(x) = <Sign_value> * <Amplitude_value> * {x - (x^3/6) + (x^5/120)} + <Offset_value>

Hope this helps.
 

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layowblue

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X^5 is very very difficult to synthesize with completely combination logic, if the clock frequency is high and the "x" bit_width is 8 or bigger.
 

rca

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Well to reduce the memory utilisation, only the 1/4 of the sinus is required.

after it is like a hardwire rom:
case (address)
begin
"0000" => data_out <= "value0";
"0001" => data_out <= "value1";
...

you replaced the value0/value1/... with your sinus text value.
you have an small state machine to go through all this value by incrementing/decrementing "addr", and a data_out manipulation to inverted or not it (as the memory contains only the 1/4 of the sinus).
 

dpaul81

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X^5 is very very difficult to synthesize with completely combination logic, if the clock frequency is high and the "x" bit_width is 8 or bigger.

I agree with you!
I had used it as a simulation model only. Something like a soft fn. gen for my other modules.
 

FvM

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I have generated the values for my sine wave... I dont know how to insert the txt file in my verilog code...
Most synthesis tools support the system tasks $readmemb (read binary file) and $readmemh (readhex file) to initialize ROM or RAM tables. $fopen/$fread for text files are usually only available for simulation purposes.

A straightforward way to generate a sine lookup table is a to use the $sin function in an initial block.
 

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