First of all this should have been posted in the ASIC Design Methodologies and Tools (Digital) forum.
Start with the ARM AHB spec first and understand it.
A two master and two slave scenario is relatively simple. You must 1st understand how an arbiter (the arbiter decides which master has control of the slaves) and address decoder (this is required to write/read slave specific data) works and how they are coded in RTL. Once you understand these, writing an RTl for the interconnect matrix shouldn't be difficult.
As someone has already mentioned, nobody will give you the here. Shows us what you have done, ask questions.