Hi,
Do you get any warnings, errors after synthesis?
What synthesis tool are you using?
What device/technology are you targeting?
About the clock, I think you can not guarantee that your outputs are going to be estable, all of them, at the same time, altough I see that you are only changing 32 bits per write. And, of course, depends of the downstream device which is sampling them, and also depends of how fast you toggle your inputs.
With a clock is EASIER to perform a timing analisys and constraint your design but if you don't want to use a clock you'll have your reasons.
As arena_yang said if this module is used at top level you need a device with a number of user IO pins > 422.
Regards,
-Maestor