Logic state for output voltage levels for 130nm process technology

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shashi106

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Hello,
I am performing simulation of a complex cmos circuit in Pyxis,Mentor Graphics tool 130 nm technology and I want to know what is the acceptable output voltage level for low and high logic states in 130 nm technology?
Please help.

Thanks in Advance.
 


there is no such thing as a "130nm technology". there are multiple vendora, and each offers a range of technology flavors. you need to read the documentation that comes with it and find out.
 
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