Logic levels of FPGA pins

[shaiko]

When an FPGA is given power for the first time (when the memory is blank - before first configuration) how are the I\O pins configured?
High 'Z' \ '1' \ '0' \ output \ input ?

 

[mrflibble]

I'm going to go with HI-Z, but best read the datasheet for your particular fpga.

 

[FvM]

I'm going to go with HI-Z, but best read the datasheet for your particular fpga.

That's what common sense can tell you, even without reading a datasheet. If it's not high-Z respectively input, logic signals connected to FPGA pins would be shorted, possibly damaging the driving logic or FPGA.

If reading a datasheet isn't asking too much, you'll also get to know that many FPGAs are providing weak pull-up resistors for programmable pins in unconfigured state.

 

[shaiko]

FPGAs are providing weak pull-up resistors for programmable pins in unconfigured state.

What about an FPGA pin configured as an output?
Will it still be tied to a pull up if somewhere in the code it's assigned: High 'Z' ?

some_signal <= 'Z' ;

Will the output "some_signal" simply remain floating or will it connect to a weak pullup ?

 

[FvM]

The question and answer was about unconfigured state. At this time, the FPGA can't know which pins are intended as outputs. So it can't but treat all pins the same way, except for dedicated pins with function predefined in hardware.

Once the configuration takes effect (FPGA entering "user mode") each pin acts as defined in the configuration file. Weak pull-ups are disconnected if they aren't explicitely activated in the configuration for the respective pin or defined as default for unconnected pins.