logic synthesis is to transform RTL code into gate netlist.
physical synthesis is to take account the flooplan during the synthesis to improve the drive of the std.
in logic synthesis we use some models??? can any one explain why we should go for that??????
which model we should consider i.e., wlm or zwlm??????
how we should analysis the models???
wlm, is wire load model, for you ?
zwlm, never heard.
The synthesis tool need the liberty files which contain the std cell & macro descriptions (timing, area, power) to transform the RTL in netlist.
THE synthesis tool could used the SDC (synopsys design contraints) to at least constraint the design with a create_clock..., and you could relax it with (false_path, multiple_cycle_path...).