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Location of AC coupling capacitors

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sharpsharpie

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Hi all,

I am working on a multi-board design where a simplified block diagram is shown below. The FPGA's transceiver block uses 0.95VDD and PHY uses 3.3VDD. So I need to use AC coupling caps to route SGMII between the FGPA and PHY. Data rate is 1.25Gbps and traces are impedance controlled
Capture.PNG


I've seen multiple app notes about location of the AC coupling caps (TX side, RX side, or anywhere) but none of them provide any theoretical explanation. The FPGA's datasheet says it's ok to put the caps anywhere.

In summary I think there are 4 possibilities of placing AC coupling caps.
I'm sure each option has its pros and cons. Which way is most desirable way?
Capture1.PNG
 

BradtheRad

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Usual advice says avoid long leads and avoid floating inputs. When you put a series capacitor at the end of a long wire, it creates a high-impedance antenna, permitting all kinds of EM noise and ambient mains hum to impinge on the wire, and it goes to the input.

It suggests a guideline to put the long wire on the sending device, and the series capacitor close to the input. The high-impedance condition still persists, however, and the capacitor may take some time to return to a satisfactory running state once it's exposed to unforeseeable volt levels.
 

FvM

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The capacitor placement is completely irrelevant for intraboard connections. The receivers have DC biasing, it doesn't matter how far the capacitor is from the receiver pin. Differential pair rules suggest however a symmetrical capacitor placement, in so far variant 3 and 4 are unwanted.

For interboard connections, follow the specification of the respective IO standard and chip datasheets. PCIe and USB3 are usually placing it at the TX side.
 

HasHx

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In addition to what FvM said above, I suggest placing the caps at the FPGA side, as it does not make much difference but in all cases the FPGA can be more susceptible to EMI and this should help reduce it in case of there was no signaling.
 

sharpsharpie

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I am trying to decide location of AC coupling capacitors between FPGA and PHY SGMII interface and datasheets of neither part has any useful information.

I've read some notes, like this one (http://www.sigcon.com/Pubs/news/7_08.htm) from Dr. Howard Johnson and some other posts where people providing pros of placing AC coupling caps near a transmitter.

However I've also seen many other app notes such as this one from TI, SCAA059C (http://www.ti.com/lit/an/scaa059c/s...12204&ref_url=https%3A%2F%2Fwww.google.com%2F) that have AC coupling caps located near a receiver but not providing any reason for it. Electrically is there any benefit or reason to place AC coupling caps near a receiver?

Also, I've seen some designs where caps are placed like below. If caps on transmitter side (or receiver side) is better, why would one design like below? Could there be any practical reason why below locations might provide more benefits?

enter image description here
 

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