Loading the cofiguration bitstream to FPGA

[sriharsha.hs]

Hello folks,

I am new to FPGA design. Currently working with Spartan 3AN. I want my design to automatically run in FPGA as soon as the power is up on the board.

I can use the ISP Flash for storing my configuration bit streams. After the FPGA configures, the application loaded into the FPGA can access the ISF
memory using a special design primitive called SPI_ACCESS. The control logic is implemented using the FPGA’s programmable logic resources. My question is how shall I run my actual logic in a FPGA as soon as the power is up. Because I don't want to load control logic to the FPGA every time I power up.

Please, suggest the possibilities.

Thank you.

 

[TrickyDicky]

You cant avoid configuring the FPGA on power up - it is volatile so it cannot store configuration data without power, hence needed the flash configuration. If you want one that doesnt need an external configuration, then you will need to look into something like the Altera Max V CPLD (or Xilinx equivolent).

 

[sriharsha.hs]

You cant avoid configuring the FPGA on power up - it is volatile so it cannot store configuration data without power, hence needed the flash configuration. If you want one that doesnt need an external configuration, then you will need to look into something like the Altera Max V CPLD (or Xilinx equivolent).

Hi TrickyDicky,

Thank you for the reply. Is there any interface module which is hard wired to FPGA, So, using that interface control module I can move the configuration bit streams to FPGA fabric using BPI or SPI configuration modes.

- - - Updated - - -

You cant avoid configuring the FPGA on power up - it is volatile so it cannot store configuration data without power, hence needed the flash configuration. If you want one that doesnt need an external configuration, then you will need to look into something like the Altera Max V CPLD (or Xilinx equivolent).

Hi,

If possible, can you list out the devices available which are equivalent to Altera Max V CPLD?

Thank you.

 

[TrickyDicky]

I know you can use an altera Max V loaded with a Parrallel flash loader megafunction to get the FPGA loaded quicker than standard flash configuration (you need this if you're using PCIe).

Ive only every used altera parts, so I wouldnt know the equivolent xilinx.

 

[sriharsha.hs]

I know you can use an altera Max V loaded with a Parrallel flash loader megafunction to get the FPGA loaded quicker than standard flash configuration (you need this if you're using PCIe).

Ive only every used altera parts, so I wouldnt know the equivolent xilinx.

Hi,

I guess you are doing PCIe booting. Could you please explain in more detail on how I could configure the fabric without the external configuration in the Altera Max V FPGA?

THank you

 

[TrickyDicky]

You cant. The Max V is non-volotile and contains the parrallel flash loader that can load data from parrallel flash to configure the FPGA in time for the FPGA to get configured on the PCIe bus (inside the 200ms window). With larger and newer devices this cant be done in time, but they allow you to configure the transeivers separately so they are up in time to configure on the PCIe bus.

FPGAs always need an external configuration, either from flash or from a processor.

 

[sriharsha.hs]

[QUOTE

FPGAs always need an external configuration, either from flash or from a processor.[/QUOTE]

Hi,

Does FPGA really requires the external configuration?, Is there any hardware configurable modes in FPGA which can be responsible for loading bit streams from Flash to FPGA fabric.

Thank you.

 

[aruipksni]

[QUOTE

FPGAs always need an external configuration, either from flash or from a processor.

Hi,

Does FPGA really requires the external configuration?, Is there any hardware configurable modes in FPGA which can be responsible for loading bit streams from Flash to FPGA fabric.

Thank you.[/QUOTE]

for the spartan3an there is an internal flash you can use to configure you'r device.
there are numerous modes to how it can also configure itself externaly you just need to read the documentation.
you can then upgrade it via spi i/os or configuration dedicated pins or by jtag ofcourse.
i once did the internal spi program and it worked very nice.

 

[sriharsha.hs]

Hi,

Does FPGA really requires the external configuration?, Is there any hardware configurable modes in FPGA which can be responsible for loading bit streams from Flash to FPGA fabric.

Thank you.

for the spartan3an there is an internal flash you can use to configure you'r device.
there are numerous modes to how it can also configure itself externaly you just need to read the documentation.
you can then upgrade it via spi i/os or configuration dedicated pins or by jtag ofcourse.
i once did the internal spi program and it worked very nice.[/QUOTE]

Hello aruipksni ,

Thanks for the reply sent. I really appreciate your involvement in this post. I have a doubt regarding the In system flash and CCL ( CMOS configuaration latches / SRAM). May be it sounds stupid.

Here it goes,

As per you said, I will transfer the configuration bit streams to an internal SPI Flash through JTAG. After when I power on the board how will my logic get transferred to the fabric?, do I need some external logic?
what is the difference between configuration flash and programming flash (FPGA fabric)?

I am not getting the picture clear. Please, explain me in more detail.

Replies are appreciated.

Thank you .

 

[aruipksni]

for the spartan3an there is an internal flash you can use to configure you'r device.
there are numerous modes to how it can also configure itself externaly you just need to read the documentation.
you can then upgrade it via spi i/os or configuration dedicated pins or by jtag ofcourse.
i once did the internal spi program and it worked very nice.

Hello aruipksni ,

Thanks for the reply sent. I really appreciate your involvement in this post. I have a doubt regarding the In system flash and CCL ( CMOS configuaration latches / SRAM). May be it sounds stupid.

Here it goes,

As per you said, I will transfer the configuration bit streams to an internal SPI Flash through JTAG. After when I power on the board how will my logic get transferred to the fabric?, do I need some external logic?
what is the difference between configuration flash and programming flash (FPGA fabric)?

I am not getting the picture clear. Please, explain me in more detail.

Replies are appreciated.

Thank you .[/QUOTE]

you need to set M2-0 pins to
Internal Master SPI mode "011"
then your FPGA will be configured from the internal flash. for more detailes you can read the literature.
https://www.xilinx.com/support/documentation/user_guides/ug332.pdf

 

[sriharsha.hs]

Hello aruipksni ,

Thanks for the reply sent. I really appreciate your involvement in this post. I have a doubt regarding the In system flash and CCL ( CMOS configuaration latches / SRAM). May be it sounds stupid.

Here it goes,

As per you said, I will transfer the configuration bit streams to an internal SPI Flash through JTAG. After when I power on the board how will my logic get transferred to the fabric?, do I need some external logic?
what is the difference between configuration flash and programming flash (FPGA fabric)?

I am not getting the picture clear. Please, explain me in more detail.

Replies are appreciated.

Thank you .

you need to set M2-0 pins to
Internal Master SPI mode "011"
then your FPGA will be configured from the internal flash. for more detailes you can read the literature.
https://www.xilinx.com/support/documentation/user_guides/ug332.pdf[/QUOTE]

Thanks a lot.

I will look in to that in detail .

Thank you.

 

[Ice-Tea]

If you wsh to avoid that altogether, you can turn to flash based FPGAS. CPLDs (like the MAX and Coolrunner series from Altera and Xilinx) are examples but there are more potent full fledged FPGAS available, notably from Actel/Microsemi. These are pretty much "up" as soon as you power them, often at a lower power budget too