Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

LNA design problem avago vmmk1218 noise figure and input matching

Status
Not open for further replies.

ashhadb

Newbie level 4
Joined
Jan 7, 2010
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,328
I am designing an LNA using vmmk1218 from avago. the design is based on specs by ims2011 baltimore , a design competition . I downloaded the ADS device modelfrom avago official website, I designed the bias network , but the problem

1.) is that the NFmin in the datasheet is 0.16 @2GHz (my working freq is 2.45GHz) while I get NFmin=0.02 after simulations,

2.) also I am unable to design a input matching network .... using the procedure in the lab1linearlna design pdf....

3.) for best oip3 results what is the best matching technique, p1dbmatch . . . . . .



I am attaching the project files bias point 1.5V 20mA 2.45GHz using doroid er=2.2 p1db req>3dbm gain req>13db LNAFOM=oip3/nf/dc(power)

**broken link removed**



**broken link removed**

I have updateed the attachments , there have been many views but no reply, please spare some time . . . . .
 

Attachments

  • Lab_1_Linear_LNA_design.pdf
    2.3 MB · Views: 137
  • avago.rar
    2 MB · Views: 88
Last edited:

If you want people to reply soon i would suggest you give more insight into the topology of LNA you are using instead of making people figure your question out first.
What LNA topology are you using? If you are using a common gate LNA, the input matching is pretty straightforward, it is 1/gm. so you wanna set that to the resistance value you want to match it with (Ofcourse the trade off is that, your gain for that stage will be limited since u are using the input stage for matching). A way around the gain limitation is to use a gm boosting, this introduces another design variable , so you can control matching and gain better! its always a good idea as a good designer to do the hand analysis of your circuit first! it helps a lot and the satisfaction you get when stuff works is worth the trouble of doing hand analysis first. Goodluck!
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top