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LLC HB with synchronous rectifiers can be very dodgy?

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Jun 13, 2021
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If synch rects are used with LLC, then a suitable delay must be used in the drive to the synch rect FETs. This is the case whether you are operating above or below the “upper resonant frequency”.
The attached 2 LTspice simulations (the ones with "2 diode" output, not FWB) show the perils of not using the delay (just remove the delay blocks to see it without the delays).
So, somehow, your LLC control needs to be able to spot how far above or below the “upper resonant frequency” you are in order to implement the requisite delay………AYK, the delay must be as short as possible, so as to maximise efficiency, but not so short that the situation described is violated……but the further from “upper resonant frequency” you are, the longer the delay needs to be.
The ICE2HS01G LLC controller purports to be able to always correctly assess and implement the delay. However, would you agree, its doubtful that under all conditions of load/line transients, startup, re-start, brownout, return from brownout, etc etc etc……it couldn’t possibly always properly assess and implement the delay?……its related to the reverse recovery problem in LLC’s…..and how its impossible for any controller to be able to guarantee always avoiding harsh reverse recovery……unless of course it’s the LLC controller demo’d by Infineon which purports to be able to detect reverse recovery by software before it actually happens…and then simply avoid switching the FETs during such intervals….but even that software’s true success is not truly known?.....(if it did what it said…then it would truly be a Nobel prize candidate.)
So would you agree that synch rects in LLC converters are dodgy?……….unless you have a very tame application which never has the situations such as transients etc, as listed above…..or unless you have the magic Infineon type software.

...I mean, the overvoltages etc that happen when synch rects go wrong can seriously weaken, and reduce the lifetime of, the LLC, even if they dont blow it up at the time....maybe it blows up after the warrantee period so you're OK...who knows.

This post tells you what most of the App Notes dont about reverse recovery in LLC's.....(which is the related situation to the problem with synch rects discussed here)

ICE2HS01G LLC controller


As can be seen, the attached (LTspice and jpeg) is a 2kW HB LLC with a Full Wave Bridge output. You can save power by making the bottom two output diodes synchronous……….and with a fixed 750ns (or more) delay between 2ndary synch rects and primary FET……you are fine no matter what fault conditions are encountered. (because the other diode in the FWB protects you). This is the only robust way to do synchronous FETs with an LLC converter (ie, with FWB and only make 2 of the 4 synchronous)…..other ways are OK only if you have highly complex control software and sensing in order to mitigate the ruinous electrical conditions that can come with synch rects and LLC.
I pity many who have got LLC designs which ignore the above...their field failure rate could end up being very is known, many PSU's rarely get turned ON to above 10% power in their life, so they are ok...but others...well...

So do you agree, the attached "2 out of 4" synch rects with the FWB output is the only good way for LLC with synch rects?


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I ran the "LESS_fsr" simulation and saw that the delay blocks are so slow that their outputs never go high at all. I'm assuming that's not intended?

The ICE2HS01G datasheet says it makes some adjustment to the SR timings based on the detected load, but it's basically up to users to tune these settings. I don't think they're claiming to have any magic tricks.

I don't deal much with LLC topology, but AFAIK it's always been difficult to optimize, especially when large line/load transients are involved. Adding SR to it will always be a challenge.

IMO the ideal way to control the SR FETs is by detecting the sign of the secondary current such that they behave like ideal, passive diodes. But I'm assuming there's some situations where this doesn't work.
I ran the "LESS_fsr" simulation and saw that the delay blocks are so slow that their outputs never go high at all. I'm assuming that's not intended?
Thanks, yes sorry, i was playing with it then forgot to change it back correctly.
Here it is again, with ddelay shortened..and showing bad current spikes.
As you can see the delay really needs to be to the trailing edge, not the leading edge......and even then it needs to be adjusted as the fsw changes.


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Still not seeing your point. The operating waveforms overall don't change very much if I remove the delay. And overall losses are higher with the delay. Especially in D4 in D5. Seems like they're seeing reverse breakdown when M1/M2 shut off.
That's because of reverse breakdown. And in your simulations it happens regardless of the adjustments to the SR timings.

I think the main issue is that you're operating below resonance, so everything is hard switching. Changing the period T to 16.5us or lower makes the reverse breakdown go away entirely, and reduces the overall losses by about a factor five.
Thanks thats a good point, but the situation is that AYK, an LLC can end up (after transient, overload , output short, etc etc), in this situation of hard switching......and with synch rects on the go at the makes things worse.

AYK, the following discusses that an LLC is un-robust if it doesn’t comprise the "series diode and pllel SIC diode" in the primary as follows…….

AYK, that’s cutting a very long story far too short, but the situation of the lack of robustness of synch rects with the LLC is just an extension of this. And whereas the “series diode and pllel sic fet” can mitigate the described LLC situation…there is no way of mitigating this bad situation with LLC synch rects......(unless you have 4 diode output bridge and just make 2 synchronous).
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Thanks thats a good point, but the situation is that AYK, an LLC can end up (after transient, overload , output short, etc etc), in this situation of hard switching......and with synch rects on the go at the makes things worse.
AFAIK the standard wisdom is to never wander into an operating condition where the load looks capacitive (which is what causes you to lose ZVS) by simply clamping the allowable frequency range. Extreme transient conditions (short circuit) are going to still be problematic, but in that case the controller should shut down ASAP anyways.

But anyways, I see that if I disable the SR in your simulation the huge voltage spikes go away, even when operating at fx<1. The current waveforms in the diodes suggest that the pulses to the SR FETs should be shortened, not delayed. Is that not what the ICE2HS01G does?
..Yes i think youre right, it attempts to protect.....but what you say about Shrt cct is we wish to be ready for it.....even if the controller shuts down after short cct it wont be quick enough...AYK, even one single instance of reverse recovery can severely weaken the LLC......(many dont mind as it may not happen till after the warantee period)

...AYK, Infineon claim to have LLC control software that can stop the FET ever switching on into reverse recovery........AYK, that is the level of protection needed for truly robust LLC.....they deserve Nobel prize for it, and i am amazed they havent been given , ive got a chunking great diode in series with each primary fet (+sic pllel)...dont like it..but got to have it

Also, do you agree that finally, finally!......the LLC is now a candidate for low or high voltage high power battery charging without needing an extra downstream buck or boost stage?...because with the said "series diode +pllel sic diode" and sync fets to "2 out of 4 of the FWB" output....the battery charging application can finally be done by the LLC?

The risk of getting Rev rec at low battery voltage was otherwise high.....or short battery problems.....but with the series diode its finally ok..........

Some say the PSFB is the one for battery charging, but PSFB is a "current slosher" just like the LLC and so can suffer the same without the "saviour series diode".

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